Resistive random access memory (REAM) is a new non-volatile memory type whose basic idea is that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after application of a sufficiently high voltage. The conduction path formation can arise from different mechanisms including, for example defects, metal migration. Once the filament is formed, it may be reset by being broken, which may result in high resistance or set by being re-formed, which may result in lower resistance, by an appropriately applied voltage.
FIG. 1 shows an illustration of a conventional resistive random access memory (RRAM) array 100. The RRAM cells are organized into RRAM blocks 102. Electrical connections 104 include bit lines in electrical connection to the RRAM blocks 102 for activating a particular cell in a block 102 as well as lines associated with voltage regulation and sensing. Electrical connections 106 include word lines in electrical connection to the RRAM blocks 102 for activating a particular cell in a block 102 as well as control lines and lines to provide reference voltages.
The switch from the high resistance state to the low resistance state requires the application of a potential difference to the memory cell. The switch from the low resistance state to the high resistance requires the application of another potential difference in the opposing direction to the memory cell.
FIG. 2 is a graph illustrating the current—voltage characteristics of a conventional resistive random access memory (RRAM) memory cell during set and reset. Line 202 indicates a high resistance state. At this state, the conductive filaments are broken. Upon application of a suitable positive switching voltage, conductive filaments are formed and current increases greatly with voltage in line 204. Line 206 indicates a low resistance state in which conductive filaments are present in the memory cell. Upon application of a suitable negative switching voltage, the filaments are broken and current decreases with voltage in line 208. The memory cell is then again at the low resistance state indicated by line 202.
One electrode may be pulled to ground and another electrode may be connected to a multiplexer to select with a positive voltage and a negative voltage. However, this requires a negative voltage which is not compatible with standard complementary metal oxide semiconductor (CMOS) processes.
Alternatively, one electrode may be pulled to a voltage of half a positive power supply voltage (VDD/2) and the other electrode may be connected to a multiplexer to switch between a high voltage more than VDD/2 or a low voltage less than VDD/2. However, this method requires a much higher (usually more than double) power supply voltage.